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<div class="title">xhwicap_l.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga7061e53605486f268a5e2205828d5921"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga7061e53605486f268a5e2205828d5921">XHwIcap_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;XHwIcap_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ga7061e53605486f268a5e2205828d5921"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read from the specified HwIcap device register.  <a href="group__hwicap.html#ga7061e53605486f268a5e2205828d5921">More...</a><br/></td></tr>
<tr class="separator:ga7061e53605486f268a5e2205828d5921"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8abfb8a13021622966d96781cb1a0f86"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga8abfb8a13021622966d96781cb1a0f86">XHwIcap_WriteReg</a>(BaseAddress, RegOffset, RegisterValue)&#160;&#160;&#160;XHwIcap_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="memdesc:ga8abfb8a13021622966d96781cb1a0f86"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to the specified HwIcap device register.  <a href="group__hwicap.html#ga8abfb8a13021622966d96781cb1a0f86">More...</a><br/></td></tr>
<tr class="separator:ga8abfb8a13021622966d96781cb1a0f86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the <a class="el" href="struct_x_hw_icap.html" title="The XHwIcap driver instance data. ">XHwIcap</a> device. </p>
</div></td></tr>
<tr class="memitem:gacc55662e7438a63d17100c391701bca0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#gacc55662e7438a63d17100c391701bca0">XHI_GIER_OFFSET</a>&#160;&#160;&#160;0x1C</td></tr>
<tr class="memdesc:gacc55662e7438a63d17100c391701bca0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Global Interrupt Enable Reg.  <a href="group__hwicap.html#gacc55662e7438a63d17100c391701bca0">More...</a><br/></td></tr>
<tr class="separator:gacc55662e7438a63d17100c391701bca0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4ff2b0721655b2764bff81449b368478"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga4ff2b0721655b2764bff81449b368478">XHI_IPISR_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:ga4ff2b0721655b2764bff81449b368478"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register.  <a href="group__hwicap.html#ga4ff2b0721655b2764bff81449b368478">More...</a><br/></td></tr>
<tr class="separator:ga4ff2b0721655b2764bff81449b368478"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8723cf72ecf20356371e6f6d2ce55543"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga8723cf72ecf20356371e6f6d2ce55543">XHI_IPIER_OFFSET</a>&#160;&#160;&#160;0x28</td></tr>
<tr class="memdesc:ga8723cf72ecf20356371e6f6d2ce55543"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable Register.  <a href="group__hwicap.html#ga8723cf72ecf20356371e6f6d2ce55543">More...</a><br/></td></tr>
<tr class="separator:ga8723cf72ecf20356371e6f6d2ce55543"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9f823f835a5a4cc52bb93dd31f88c62c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga9f823f835a5a4cc52bb93dd31f88c62c">XHI_WF_OFFSET</a>&#160;&#160;&#160;0x100</td></tr>
<tr class="memdesc:ga9f823f835a5a4cc52bb93dd31f88c62c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write FIFO.  <a href="group__hwicap.html#ga9f823f835a5a4cc52bb93dd31f88c62c">More...</a><br/></td></tr>
<tr class="separator:ga9f823f835a5a4cc52bb93dd31f88c62c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga880c301214287dc0231e142662bba24c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga880c301214287dc0231e142662bba24c">XHI_RF_OFFSET</a>&#160;&#160;&#160;0x104</td></tr>
<tr class="memdesc:ga880c301214287dc0231e142662bba24c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read FIFO.  <a href="group__hwicap.html#ga880c301214287dc0231e142662bba24c">More...</a><br/></td></tr>
<tr class="separator:ga880c301214287dc0231e142662bba24c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga61e8525d9e209cad45122af264f276f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga61e8525d9e209cad45122af264f276f0">XHI_SZ_OFFSET</a>&#160;&#160;&#160;0x108</td></tr>
<tr class="memdesc:ga61e8525d9e209cad45122af264f276f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size Register.  <a href="group__hwicap.html#ga61e8525d9e209cad45122af264f276f0">More...</a><br/></td></tr>
<tr class="separator:ga61e8525d9e209cad45122af264f276f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad7d94ec59e14347684d309b0b6406ab2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#gad7d94ec59e14347684d309b0b6406ab2">XHI_CR_OFFSET</a>&#160;&#160;&#160;0x10C</td></tr>
<tr class="memdesc:gad7d94ec59e14347684d309b0b6406ab2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register.  <a href="group__hwicap.html#gad7d94ec59e14347684d309b0b6406ab2">More...</a><br/></td></tr>
<tr class="separator:gad7d94ec59e14347684d309b0b6406ab2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad582c2c3fe5aa1d83b43dc7a0d243da8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#gad582c2c3fe5aa1d83b43dc7a0d243da8">XHI_SR_OFFSET</a>&#160;&#160;&#160;0x110</td></tr>
<tr class="memdesc:gad582c2c3fe5aa1d83b43dc7a0d243da8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Register.  <a href="group__hwicap.html#gad582c2c3fe5aa1d83b43dc7a0d243da8">More...</a><br/></td></tr>
<tr class="separator:gad582c2c3fe5aa1d83b43dc7a0d243da8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d5e8341edaacfbd2e50e6d348ad8131"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga2d5e8341edaacfbd2e50e6d348ad8131">XHI_WFV_OFFSET</a>&#160;&#160;&#160;0x114</td></tr>
<tr class="memdesc:ga2d5e8341edaacfbd2e50e6d348ad8131"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write FIFO Vacancy Register.  <a href="group__hwicap.html#ga2d5e8341edaacfbd2e50e6d348ad8131">More...</a><br/></td></tr>
<tr class="separator:ga2d5e8341edaacfbd2e50e6d348ad8131"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9bc6d60763a4589772fbab9611444a76"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga9bc6d60763a4589772fbab9611444a76">XHI_RFO_OFFSET</a>&#160;&#160;&#160;0x118</td></tr>
<tr class="memdesc:ga9bc6d60763a4589772fbab9611444a76"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read FIFO Occupancy Register.  <a href="group__hwicap.html#ga9bc6d60763a4589772fbab9611444a76">More...</a><br/></td></tr>
<tr class="separator:ga9bc6d60763a4589772fbab9611444a76"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device Global Interrupt Enable Register (GIER) bit definitions</div></td></tr>
<tr class="memitem:ga312f920dfd13871dfc397bb734e81542"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga312f920dfd13871dfc397bb734e81542">XHI_GIER_GIE_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:ga312f920dfd13871dfc397bb734e81542"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt enable Mask.  <a href="group__hwicap.html#ga312f920dfd13871dfc397bb734e81542">More...</a><br/></td></tr>
<tr class="separator:ga312f920dfd13871dfc397bb734e81542"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">HwIcap Device Interrupt Status/Enable Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p><b> Interrupt Status Register (IPISR) </b></p>
<p>This register holds the interrupt status flags for the device. These bits are toggle on write.</p>
<p><b> Interrupt Enable Register (IPIER) </b></p>
<p>This register is used to enable interrupt sources for the device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt.</p>
<p>IPISR/IPIER registers have the same bit definitions and are only defined once. </p>
</div></td></tr>
<tr class="memitem:gae940123f31edca885cce128466074fbd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#gae940123f31edca885cce128466074fbd">XHI_IPIXR_RFULL_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gae940123f31edca885cce128466074fbd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read FIFO Full.  <a href="group__hwicap.html#gae940123f31edca885cce128466074fbd">More...</a><br/></td></tr>
<tr class="separator:gae940123f31edca885cce128466074fbd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga47f9b5b4f4e16c810064acf5ce674575"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga47f9b5b4f4e16c810064acf5ce674575">XHI_IPIXR_WEMPTY_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga47f9b5b4f4e16c810064acf5ce674575"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write FIFO Empty.  <a href="group__hwicap.html#ga47f9b5b4f4e16c810064acf5ce674575">More...</a><br/></td></tr>
<tr class="separator:ga47f9b5b4f4e16c810064acf5ce674575"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae64834b12bee384ff441cf4ca68b060b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#gae64834b12bee384ff441cf4ca68b060b">XHI_IPIXR_RDP_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gae64834b12bee384ff441cf4ca68b060b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read FIFO half full.  <a href="group__hwicap.html#gae64834b12bee384ff441cf4ca68b060b">More...</a><br/></td></tr>
<tr class="separator:gae64834b12bee384ff441cf4ca68b060b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d51a2ca2954770e68e8304c6d45a797"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga3d51a2ca2954770e68e8304c6d45a797">XHI_IPIXR_WRP_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga3d51a2ca2954770e68e8304c6d45a797"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write FIFO half full.  <a href="group__hwicap.html#ga3d51a2ca2954770e68e8304c6d45a797">More...</a><br/></td></tr>
<tr class="separator:ga3d51a2ca2954770e68e8304c6d45a797"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga796c30e8bebadbe5c18ce0af9b10d30a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga796c30e8bebadbe5c18ce0af9b10d30a">XHI_IPIXR_ALL_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:ga796c30e8bebadbe5c18ce0af9b10d30a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask of all interrupts.  <a href="group__hwicap.html#ga796c30e8bebadbe5c18ce0af9b10d30a">More...</a><br/></td></tr>
<tr class="separator:ga796c30e8bebadbe5c18ce0af9b10d30a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Register (CR)</div></td></tr>
<tr class="memitem:ga776ac9dc4020f86bab9c5b1fd9221dd1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga776ac9dc4020f86bab9c5b1fd9221dd1">XHI_CR_SW_ABORT_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga776ac9dc4020f86bab9c5b1fd9221dd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Abort current ICAP Read/Write.  <a href="group__hwicap.html#ga776ac9dc4020f86bab9c5b1fd9221dd1">More...</a><br/></td></tr>
<tr class="separator:ga776ac9dc4020f86bab9c5b1fd9221dd1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga50e289c4313fa405cf086df7ce901a1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga50e289c4313fa405cf086df7ce901a1b">XHI_CR_SW_RESET_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga50e289c4313fa405cf086df7ce901a1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">SW Reset Mask.  <a href="group__hwicap.html#ga50e289c4313fa405cf086df7ce901a1b">More...</a><br/></td></tr>
<tr class="separator:ga50e289c4313fa405cf086df7ce901a1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafd19f105fe87bc06e8970c46f2f23508"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#gafd19f105fe87bc06e8970c46f2f23508">XHI_CR_FIFO_CLR_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gafd19f105fe87bc06e8970c46f2f23508"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO Clear Mask.  <a href="group__hwicap.html#gafd19f105fe87bc06e8970c46f2f23508">More...</a><br/></td></tr>
<tr class="separator:gafd19f105fe87bc06e8970c46f2f23508"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5f79a1af0d4909378342da1723568653"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga5f79a1af0d4909378342da1723568653">XHI_CR_READ_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga5f79a1af0d4909378342da1723568653"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read from ICAP to FIFO.  <a href="group__hwicap.html#ga5f79a1af0d4909378342da1723568653">More...</a><br/></td></tr>
<tr class="separator:ga5f79a1af0d4909378342da1723568653"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaef1da3487a4b5b56304445dd5892855b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#gaef1da3487a4b5b56304445dd5892855b">XHI_CR_WRITE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaef1da3487a4b5b56304445dd5892855b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write from FIFO to ICAP.  <a href="group__hwicap.html#gaef1da3487a4b5b56304445dd5892855b">More...</a><br/></td></tr>
<tr class="separator:gaef1da3487a4b5b56304445dd5892855b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Status Register (SR)</div></td></tr>
<tr class="memitem:ga70dd605f5c61f0d4dca8f7d2c7818b96"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga70dd605f5c61f0d4dca8f7d2c7818b96">XHI_SR_CFGERR_N_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga70dd605f5c61f0d4dca8f7d2c7818b96"><td class="mdescLeft">&#160;</td><td class="mdescRight">Config Error Mask.  <a href="group__hwicap.html#ga70dd605f5c61f0d4dca8f7d2c7818b96">More...</a><br/></td></tr>
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<tr class="memitem:gab20344d8715b57430612cbee984dc22e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#gab20344d8715b57430612cbee984dc22e">XHI_SR_DALIGN_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
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<tr class="memitem:gabd2efa3b995368421322945fcf4a0193"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#gabd2efa3b995368421322945fcf4a0193">XHI_SR_RIP_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
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<tr class="memitem:ga4e0a65580d8d9e4ea6a0df1a65c5308c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga4e0a65580d8d9e4ea6a0df1a65c5308c">XHI_SR_IN_ABORT_N_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
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<tr class="memitem:ga5f6dfed1a6cda2d244f7b58ccf734eb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga5f6dfed1a6cda2d244f7b58ccf734eb3">XHI_SR_DONE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
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<tr class="memitem:ga4b189772fde4c6ca3bc0c20b7b1fc3af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__hwicap.html#ga4b189772fde4c6ca3bc0c20b7b1fc3af">XHI_SR_EOS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
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